1. Field of the Invention
Aspects of the present invention relate to a method of fabricating a thin film transistor. More particularly, aspects of the present invention relate to a method of fabricating a complimentary metal-oxide semiconductor (CMOS) thin film transistor in which, in order to remove metal catalysts remaining in a polysilicon layer after crystallizing an amorphous silicon layer to the polysilicon layer using a super grain silicon (SGS) crystallization method, when impurities such as phosphorus (P) are implanted into source and drain regions of a p-type metal-oxide semiconductor (PMOS) thin film transistor, the impurities are also simultaneously implanted into source and drain regions of an n-type metal-oxide semiconductor (NMOS) thin film transistor and a substrate is annealed. Accordingly, an amount of metal catalyst remaining in a semiconductor layer is minimized and its manufacturing process is simplified.
2. Description of the Related Art
A complimentary metal-oxide semiconductor (CMOS) thin film transistor includes a p-type metal-oxide semiconductor (PMOS) thin film transistor and an n-type metal-oxide semiconductor (NMOS) thin film transistor. The CMOS thin film transistor is advantageous in implementing various circuits and systems that are difficult to realize using only one of the PMOS or NMOS thin film transistor.
FIGS. 1A to 1D are cross-sectional views illustrating a related art method of fabricating a CMOS thin film transistor. As shown in FIG. 1A, a substrate 10 including a PMOS region P and an NMOS region N is provided. A PMOS semiconductor layer 21 and an NMOS semiconductor layer 23 are respectively formed on the PMOS and NMOS regions P and N using a first mask (not shown). A gate insulating layer 30 is formed on the semiconductor layers 21 and 23. A gate conductive layer 40 is deposited on the gate insulating layer 30. A photoresist pattern 91 is formed on the gate conductive layer 40 using a second mask (not shown), and the gate conductive layer 40 is etched using the photoresist pattern 91 as a mask.
Accordingly, a PMOS gate electrode 41 overlapping the PMOS semiconductor layer 21 is formed. Meanwhile, a gate conductive layer 40 is shielded by the photoresist pattern 91 and remains in the NMOS region N. Then, a high concentration of p-type impurities are implanted at respectively in regions P and N using the photoresist pattern 91 and the PMOS gate electrode 41 as masks to form source and drain regions 21a and 21c in the PMOS semiconductor layer 21. A non-doped region disposed between the source and drain regions 21a is defined as a channel region 21b. 
As shown in FIG. 1B, the photoresist pattern 91 (see FIG. 1A) is removed, and a new photoresist pattern 93 is formed using a third mask (not shown). The gate conductive layer 40 (see FIG. 1A) is etched in both P and N regions using the photoresist pattern 93 as a mask to form an NMOS gate electrode 43 overlapping the NMOS semiconductor layer 23. Then, n-type impurities are implanted at a low concentration using the photoresist pattern 93 and the NMOS gate electrode 43 as masks, thereby forming low-concentration impurity regions 23a and 23c in the NMOS semiconductor layer 23. A non-doped region disposed between the low-concentration impurity regions 23a is defined as a channel region 23b. 
As shown in FIG. 1C, the photoresist pattern 93 (see FIG. 1B) is removed, and a new photoresist pattern 95 is formed using a fourth mask (not shown). A high concentration of n-type impurities are implanted using the photoresist pattern 95 as a mask to form high-concentration impurity regions 23a-1 in the NMOS semiconductor layer 23. At this time, the low-concentration impurity regions 23a-2 remain on sides of each of the high-concentration impurity regions 23a-1 to form lightly doped drain (LDD) regions (i.e., the low-concentration impurity regions 23a-2).
Referring to FIG. 1D, the photoresist pattern 95 (see FIG. 1C) is removed to expose the gate electrodes 41 and 43. An interlayer insulating layer 50 is formed on the exposed gate electrodes 41 and 43, and contact holes exposing ends of the semiconductor layers 21 and 23 are formed in the interlayer insulating layer 50 using a fifth mask (not shown). Then, PMOS source and drain electrodes 61 and NMOS source and drain electrodes 63 in contact with the ends of the semiconductor layers 21 and 23 are formed through the contact holes using a sixth mask (not shown), respectively.
However, the PMOS and NMOS thin film transistors are formed on a single substrate to form the related art CMOS thin film transistor, requiring numerous processes or operations. In particular, since the LDD regions 23a-2 are formed in order to solve reliability problems (such as a hot carrier effect caused by leakage current) and to enable miniaturization of the NMOS thin film transistor, the number of masks for implementing the CMOS thin film transistor is increased, the process is made complicated, and the process time is increased, thereby increasing manufacturing cost.